* Qualcomm Technologies, Inc. MSM FD

Face detection hardware block.
The Face Detection Hardware Block will offload processing
on the host and also reduce power consumption.
Supports:
Front and back camera face detection concurrently.
Sizes: QVGA, VGA, WQVGA, WVGA at 20 pix minimum face size.

Required properties:

- compatible:
    - "qcom,face-detection"
- reg: offset and length of the register set for the device.
- reg-names: should specify relevant names to each reg property defined.
    - "fd_core" - FD CORE hardware register set.
    - "fd_misc" - FD MISC hardware register set.
    - "fd_vbif" - FD VBIF hardware register set.
- interrupts: should contain the fd interrupts. From fd cores with
  revisions 0x10010000 and higher, power collapse sequence is required.
  Face detection misc irq is needed to perform power collapse.
- interrupt-names: should specify relevant names to each interrupts
  property defined.
- vdd-supply: phandle to GDSC regulator controlling face detection hw.
- clocks: list of entries each of which contains:
    - phandle to the clock controller.
    - macro containing clock's name in hardware.
- clock-names: should specify relevant names to each clocks
  property defined.

Optional properties:

- clock-rates: should specify clock rates in Hz to each clocks
  property defined.
  If we want to have different operating clock frequencies we can define
  rate levels. They should be defined in incremental order.
- qcom,bus-bandwidth-vectors: Specifies instant and average bus bandwidth
  vectors per clock rate.
  Each of entries contains:
  - ab. Average bus bandwidth (Bps).
  - ib. Instantaneous bus bandwidth (Bps).
- mmagic-vdd-supply: phandle to GDSC regulator controlling mmagic.
- camss-vdd-supply: phandle to GDSC regulator controlling camss.
- qcom,fd-core-reg-settings: relative address offsets and value pairs for
  FD CORE registers and bit mask.
  Format: <reg_addr_offset reg_value reg_mask>
- qcom,fd-misc-reg-settings: relative address offsets and value pairs for
  FD MISC registers and bit mask.
  Format: <reg_addr_offset reg_value reg_mask>
- qcom,fd-vbif-reg-settings: relative address offsets and value pairs for
  FD VBIF registers and bit mask.
  Format: <reg_addr_offset reg_value reg_mask>

Example:

    qcom,fd@fd878000 {
        compatible = "qcom,face-detection";
        reg = <0xfd878000 0x800>,
              <0xfd87c000 0x800>,
              <0xfd860000 0x1000>;
        reg-names = "fd_core", "fd_misc", "fd_vbif";
        interrupts = <0 316 0>;
        interrupt-names = "fd";
        mmagic-vdd-supply = <&gdsc_mmagic_camss>;
        camss-vdd-supply = <&gdsc_camss_top>;
        vdd-supply = <&gdsc_fd>;
        qcom,vdd-names = "mmagic-vdd", "camss-vdd", "vdd";
        clocks = <&clock_mmss clk_mmss_mmagic_ahb_clk>,
                <&clock_gcc  clk_mmssnoc_axi_clk>,
                <&clock_mmss clk_mmagic_camss_axi_clk>,
                <&clock_mmss clk_camss_top_ahb_clk>,
                <&clock_mmss clk_fd_core_clk_src>,
                <&clock_mmss clk_fd_core_clk>,
                <&clock_mmss clk_fd_core_uar_clk>,
                <&clock_mmss clk_fd_ahb_clk>,
                <&clock_mmss clk_smmu_cpp_axi_clk>,
                <&clock_mmss clk_camss_ahb_clk>,
                <&clock_mmss clk_camss_cpp_axi_clk>,
                <&clock_mmss clk_camss_cpp_vbif_ahb_clk>,
                <&clock_mmss clk_smmu_cpp_ahb_clk>;
        clock-names = "mmss_mmagic_ahb_clk", "mmssnoc_axi_clk" ,
                        "mmagic_camss_axi_clk", "camss_top_ahb_clk",
                        "fd_core_clk_src", "fd_core_clk",
                        "fd_core_uar_clk", "fd_ahb_clk",
                        "smmu_cpp_axi_clk", "camss_ahb_clk",
                        "camss_cpp_axi_clk", "cpp_vbif_ahb_clk",
                         "smmu_cpp_ahb_clk";
        clock-rates = <0 0 0 0 400000000 400000000 400000000 80000000 0 0 0 0 0>;
        qcom,bus-bandwidth-vectors = <13000000 13000000>,
            <45000000 45000000>,
            <90000000 90000000>;
        qcom,fd-vbif-reg-settings = <0x20 0x10000000 0x30000000>,
            <0x24 0x10000000 0x30000000>,
            <0x28 0x10000000 0x30000000>,
            <0x2c 0x10000000 0x30000000>;
        qcom,fd-misc-reg-settings = <0x20 0x2 0x3>,
            <0x24 0x2 0x3>;
        qcom,fd-core-reg-settings = <0x8 0x20 0xffffffff>;
    };
